1. Field of the Invention
The present invention relates to a method for making a correction to pattern data and a method for manufacturing semiconductor devices, and particularly to the method for making the correction to pattern data affected by a proximity effect when a pattern is formed on a photomask or wafer and the method for manufacturing semiconductor devices using the above method.
2. Description of the Related Art
In recent years, patterns to be formed by photolithography employed in processes of manufacturing leading-edge semiconductor devices are being made fine and highly-integrated. As a result, a problem occurs in that, in the formation of a pattern with an exposure wavelength or less, due to an adverse influence by a proximity effect, a shape of a mask pattern using a photomask (hereinafter simply referred to as a “mask”) does not coincide with that of a resist pattern obtained by transferring the mask pattern on a wafer.
Also, in the etching process for microfabrication of a front-end layer using a resist pattern on which the mask pattern has been transferred, due to a loading effect which leads to variations in a conversion difference caused by a difference in a pattern shape and a pattern density, a phenomenon occurs that a shape of a resist pattern does not coincide with that of a microfabricated pattern for the front-end layer obtained by the selective etching process.
To solve this problem and to obtain a pattern having a desired dimension and shape, an OPC (Optical Proximity Correction) technology in which a required amount of correction is added to mask pattern data is being employed generally in recent years. To obtain an effect of the OPC technology, it is necessary that a difference between a finally-obtained dimension of a mask pattern and a dimension in mask pattern data is made as small as possible. In the formation of a mask to be used for manufacturing recent leading-edge semiconductor devices in particular, very extremely high accuracy in its linearity, in difference of pattern density, or the like is required. However, at present, it is difficult to satisfy the demand for such extremely high accuracy only by improvement of mask producing processes. This holds true for manufacturing a mask using a nega-type resist in particular. The process of manufacturing a mask using a nega-type resist is employed when a mask for a gate layer requiring extremely high accuracy is produced, thus presenting a serious problem.
A method for correcting such a dimensional error by using the OPC technology is disclosed in, for example, Japanese Unexamined Patent Publication No. 2003-195478. In this method, so-called rule-based OPC technology is applied to a mask process. According to this method, a correlation between a space dimension among adjacent patterns and a dimensional change in a pattern itself is first determined and, by using this result, a necessary dimensional correction is made to mask pattern data.
However, the conventional method disclosed in Japanese Unexamined Patent Publication No. 2003-195478 has a problem that the process in the method has a favorable correcting effect on a simple pattern if including only a line pattern and space, but adversely affects a pattern having a complicated layout.